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| www..com MOTOROLA Order Number: MC145423/D Rev. 0, 8/24/00 Semiconductor Products Sector MC145423 Product Preview Universal Digital Loop Transceiver (UDLT-3) Pin Selectable Master/Slave Limited Distance Modem The MC145423 is a CMOS integrated circuit designed to be one of the major building blocks in digital subscriber voice/data telephone systems and remote data acquisition and control systems. The UDLT-3 incorporates into one device, all the functionality of the MC145421 (ISDN UDLT-2 master), MC145425 (ISDN UDLT-2 slave), MC145422 (UDLT-1 master), and MC145426 (UDLT-1 slave). Since these modes/functions are pin selectable, the MC145423 can be used in telephone switch line cards, as well as remote digital telsets or data terminals. * VDD = 4.5 V to 5.5 V * 28-Pin SOIC and TSSOP Packages * Protocol Independent * Pin Controlled Power-Down * LI Sensitivity Control in Master Mode * 2.048 MHz Output in Slave Mode UDLT-2 Features * Synchronous Full Duplex 160 kbps Voice and Data Communications in a 2B+2D Format for ISDN Compatibility * Provides CCITT Basic Access Data Transfer Rate (2B+D) for ISDNs on a Single Twisted Pair Up to 1 km on 26 AWG or Larger Cable UDLT-1 Features * Pin Controlled Loopback * Automatic Power-Up/Down (Slave) * Full Duplex Synchronous 64 kbps Voice/Data Channel and Two 8 kbps Signaling Data Channels Over One 26 AWG Wire Pair Up to 2 km DW SUFFIX SOIC CASE 751F DT SUFFIX TSSOP CASE 1168 ORDERING INFORMATION MC145423DW MC145423DT SOIC Package TSSOP Package This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2000. All rights reserved. MC145423 PIN ASSIGNMENT VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK/8kHz SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD MASTER/SLAVE LO1 LO2 Rx RE2/BCLK RE1/CLKOUT LI SENS/2.048 MHz TDC-RDC/XTALout CCI/XTALin MSI/TONE EN1-TE1 EN2-TE2/SIE/B1B2 Tx 28-PIN SOIC/TSSOP PACKAGES 2 TELECOMMUNICATIONS MC145423 BLOCK DIAGRAM SDCLK/8kHz MODULATOR LO1 B1 B2 D1 D2 LO2 D2 BUFFER SE LATCH REGISTER LOGIC D1 BUFFER SDI2 SDI1 RE2/ BCLK Rx B2 BUFFER CCI/XTALIn (TDC-RDC)/ XTALout OSC CLKOUT BCLK Mu/A B1 BUFFER RE1/ CLKOUT SE/ (Mu/A) MSI/TONE MOD TRI/SQ FRAME 10/20 MASTER/ SLAVE LI SENS/ 2.048 MHz SEQUENCE AND CONTROL SE LATCH EN2-TE2 SE LATCH EN1-TE1 SE LATCH TDC/RDC VD CONTROL D2 REGISTER LOGIC D1 B2 B2 BUFFER B1 B1 BUFFER D1 BUFFER BCLK LB PD VD D2 BUFFER SDO2 SDO1 LI DEMODULATOR Vref Tx EN2-TE2/ SIE EN1-TE1 TELECOMMUNICATIONS 3 MC145423 ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS) Rating DC Supply Voltage Voltage, Any Pin to VSS DC Current, Any Pin (Excluding VDD, VSS) Operating Temperature Storage Temperature Symbol VDD - VSS V I TA Tstg Value -0.5 to 6 -0.5 to VDD + 0.5 10 -40 to 85 -85 to 150 Unit V V mA C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic level (e.g., either VSS or VDD). RECOMMENDED OPERATING CONDITIONS (TA = -40 to 85C) Parameter DC Supply Voltage Power Dissipation (PD = VDD) Power Dissipation (PD = VSS) Frame Rate CCI CLK Frequency (MSI = 8 kHz) UDLT-1 (CCI = 256 x MSI) UDLT-2 Frame Rate Slip* Data Clock Rate (Master Mode) UDLT-1 UDLT-2 SDCLK (UDLT-2 Only) Modulation Baud Rate UDLT-1 UDLT-2 LO1, LO2 -- -- -- -- 256 512 TDC-RDC 64 128 16 -- -- -- 4100 4100 4100 kHz kHz VDD = 5 V VDD = 5 V Pins VDD VDD VDD MSI CCI -- -- -- 2.048 8.192 -- -- 8.29 0.25 % kHz Min 4.5 -- -- 7.9 Typ -- -- -- 8.0 Max 5.5 80 80 8.1 Unit V mW mW kHz MHz * The slave's crystal frequency divided by 512 (UDLT-1) or 1024 (UDLT-2), must equal the master's MSI frequency 0.25% for optimum operation. 4 TELECOMMUNICATIONS MC145423 DIGITAL CHARACTERISTICS (VDD = 5 V 10%, TA = -40 to 85C, Unless Otherwise Stated) Parameter Input High Level Input Low Level Input Current (Digital Pins) Input Current LI Input Capacitance Output High Current (Excluding Tx and PD) Output Current Low (Excluding Tx and PD) Tx Output High Current Tx Output Low Current PD Output High Current -- Slave Mode* PD Output Low Current -- Slave Mode* Tx, SDO1, SDO2, and VD Three-State Current XTAL Output High Current XTAL Output Low Current VOH = VDD - 0.5 V VOL = 0.4 V VOH = VDD - 0.5 V VOL = 0.4V VOH = 2.5 V VOH = VDD - 0.5 V VOL = 0.4 V VOL = 0.8 V VOH = 2.5 V VOH = VDD - 0.5 V VOL = 0.8 V VOL = 0.4 V Min VDD x 0.7 -- -- -- -- -1.6 1.6 -3.4 -2.5 2.5 3.5 -90 -10 100 60 -- -450 450 Max -- VDD x 0.3 1.0 100 7.5 -- -- -- -- -- -- -- -- -- -- 10.0 -- -- Unit V V A A pF mA mA mA mA A A A A A * To overdrive PD from a low level to 3.5 V, or a high level to 1.5 V requires a minimum of 800 A drive capability. ANALOG CHARACTERISTICS (VDD = 5 V 10%, TA = -40 to 85C) Parameter Modulation Differential Amplitude (RL = 440 ) Modulation Differential Offset Vref Voltage, Typically 9/20 x (VDD - VSS) PCM Tone Level Demodulator Input Amplitude* Demodulator Input Impedance (LI to Vref) * The input level into the demodulator to reliably demodulate incoming bursts. Input referenced to Vref. Min LO1 to LO2 4.5 0 2.0 -22 0.05 50 Max 6.0 40 2.5 -18 2.5 300 Unit Vp-p mV V dBm Vpeak k TELECOMMUNICATIONS 5 MC145423 MASTER SWITCHING CHARACTERISTICS (VDD = 5 V 10%, TA = -40 to 85C, CL = 50 pF) Parameter Input Rise Time: All Digital Inputs Input Fall Time: All Digital Inputs Pulse Width: TDC, RDC, RE1, RE2, MSI, SDCLK (UDLT-2) CCI Duty Cycle Propagation Delay: MSI to SDO1, SDO2, VD (PD = VDD) TDC to Tx MSI, TE1, TE2, RE1, RE2 to TDC-RDC Setup Time TDC-RDC to MSI, TE1, TE2, RE1, RE2, Hold Time Rx to TDC-RDC Setup Time Rx to TDC-RDC Hold Time SDI1, SDI2 to MSI Setup Time SDI1, SDI2 to MSI Hold Time MSI Rising Edge to First SDCLK Falling Edge (UDLT-2 Only) TE Rising Edge to First Tx Data Bit Valid TDC-RDC Rising Edge to Tx Data Bits 2 - 8 Valid TE1,TE2 Falling Edge to Tx High Impedance SDCLK Rising Edge to SDO1, SDO2 Bit Valid (UDLT-2 Only) SDI1, SDI2 Data Setup (Data Valid Before SDCLK Falling Edge) (UDLT-2 Only) SDI1, SDI2 Data Hold (Data Valid After SDCLK Falling Edge) (UDLT-2 Only) PD, LB Setup (PD, LB Valid Before MSI Rising Edge) PD, LB Hold (PD, LB Valid After MSI Rising Edge) Figure No. Symbol tr tf tp 90 tw2(H,L) tPLH, tPHL tsu3 th5 tsu5 th1 tsu2 th2 tP1LH tsu6 tsu7 tdly tsu8 tsu9 th3 tsu10 th4 45 -- -- 20 50 30 30 30 30 -- -- -- -- -- 50 20 50 20 -- 55 50 50 -- -- -- -- -- -- 50 50 50 70 135 -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns % ns Min -- -- Max 2 2 Unit s s ns 6 TELECOMMUNICATIONS MC145423 SLAVE SWITCHING CHARACTERISTICS (VDD = 5 V 10%, TA = -40 to 85C, CL = 50 pF) Parameter Input Rise Time: All Digital Inputs Input Fall Time: All Digital Inputs Clock Output Pulse Width: BCLK Crystal Frequency Propagation Delay Times: EN1, EN2, TE1 Rising to BCLK (TONE = VDD) EN1, EN2, TE1 Rising to BCLK (TONE = VSS) BCLK to EN1, EN2, TE1 Falling RE1 Rising to BCLK (UDLT-1) RE1 Falling to BCLK (TONE = VDD) (UDLT-1) RE1 Falling to BCLK (TONE = VSS) (UDLT-1) BCLK to Tx TE1,TE2 to SDO1, SDO2 Rx to BCLK Setup Time Rx to BCLK Hold Time SDI1, SDI2 to TE Setup Time SDI1, SDI2 to TE Hold Time EN1, EN2 Rising Edge to DCLK Rising Edge (UDLT-2) EN1, EN2 Rising Edge to First Tx Data Bit Valid BCLK Rising Edge to Tx Data Bits 2 - 8 Valid DCLK Pulse Width High (UDLT-2) DCLK Pulse Width Low (UDLT-2) DCLK Rising Edge to SDO1, SDO2 (UDLT-2) SDI1, SDI2 Setup (SDI1, SDI2 Valid Before DCLK Falling Edge) (UDLT-2) SDI1, SDI2 Hold (SDI1, SDI2 Valid After DCLK Falling Edge) (UDLT-2) EN1, TE1 Rising Edge to VD Valid Figure No. Symbol tr tf tw(H,L) fx1 tp1 tp1 tp2 tp3 tp4 tp4 tp5 tp6 tsu5 th1 tsu6 th2 tPHL tdly1 tsu7 tw(H) tw(L) tdly2 tsu9 th3 tdly3 Min -- -- 3.66 4.086 -50 300 -- -- -50 300 -- -- 30 30 30 30 -- -- -- 31 31 -- 10 -- -- Max 2 2 4.15 4.1 175 400 20 20 50 400 50 50 -- -- -- -- 30 30 -40 31.5 31.5 30 -- 30 30 ns ns ns ns ns ns ns s s ns ns ns ns Unit s s s MHz ns SE PIN TIMING Parameter LB, PD Hold (LB, PD Valid After SE Falling Edge) SDO1, SDO2, VD High Impedance After SE Falling Edge SDO1, SDO2, VD Valid After SE Rising Edge LB, PD Setup (LB, PD Valid Before SE Rising Edge) Figure No. Symbol th tdly1 tdly2 tsu Min 10 -- 30 25 Max -- 40 -- -- Unit ns ns ns ns TELECOMMUNICATIONS 7 8 tw(H) tp5 tw(L) tp2 tp3 tp4 B13 tsu5 DON'T CARE B11 B12 B13 B14 B15 th1 B16 B17 B18 B14 B15 B16 B17 B18 HIGH IMPEDANCE VALID MC145423 BCLK tp1 TE1 RE1 Tx B11 B12 Rx Figure 1. UDLT-1 Slave Timing Nonsynchronous TELECOMMUNICATIONS tsu6 SDI1, SDI2 th2 SDO1, SDO2 tp6 VD tdly3 tw(H) BCLK tp5 tw(L) tp2 tp1 TE1 tp3 tp4 RE1 B13 tsu5 B12 th1 B13 B14 B15 B16 B17 B18 DON'T CARE B14 B15 B16 B17 B18 HIGH IMPEDANCE Tx B11 B12 Rx B11 Figure 2. UDLT-1 Slave Timing Synchronous TELECOMMUNICATIONS VALID tsu6 SDI1, SDI2 th2 SDO1, SDO2 tp6 VD tdly3 MC145423 9 10 tw(H) tp5 tw(L) tp2 tp1 tdly1 B12 B22 B23 tsu5 B12 B18 B22 tw(H) th1 B13 B14 B15 B16 B17 B21 B23 B24 B25 B26 tw(L) B27 B28 B11 B13 B14 B15 B16 B17 B18 B21 tsu7 B24 B25 B26 B27 B2 B18 B11 tdly2 B1 tsu9 B1 th3 VALID B2 B2 MC145423 BCLK tp1 EN1 EN2 Tx B11 Rx B11 tPHL Figure 3. UDLT-2 Slave Timing TELECOMMUNICATIONS SDCLK SDO1, SDO2 SDI1, SDI2 tdly3 VD tp MSI tsu3 tsu3 tw2 th5 CCI, TDC/ RDC th5 tw2 th5 tsu3 TE1 tPLH/tPHL B11 tp B12 B13 B14 B15 B16 B17 B18 HIGH IMPEDANCE Tx RE1 th1 tsu5 DON'T CARE B11 B12 B13 B14 B15 B16 B17 B18 DON'T CARE Figure 4. UDLT-1 Master Timing TELECOMMUNICATIONS VALID DON'T CARE VALID Rx tPLH/tPHL SDO1, SDO2 th2 VALID tsu2 SDI1, SDI2 VALID tPLH/tPHL VD MC145423 11 12 tw2 th5 th5 tw2 tsu3 th5 tsu6 B11 tp B12 B13 B14 B15 B16 B17 B18 tsu7 tdly th1 tsu5 B11 tP1LH B12 B13 B14 tw2 B15 B16 B17 B18 tsu8 B1 tsu9 th3 B1 DON'T CARE B2 DON'T CARE B2 tw2 VALID DON'T CARE MC145423 tp MSI th5 TDC/RDC TE1/TE2 Tx RE1/ RE2 Rx Figure 5. UDLT-2 Master Timing TELECOMMUNICATIONS SDCLK tdly3 /tPHL PLH SDO1, SDO2 SDI1, SDI2 DON'T CARE tPLH/tPHL VD tsu10 th4 PD/LB VALID B1 MC145423 SE th LB, PD PREVIOUS STATE INTERNALLY LATCHED tsu SDO1, SDO2, VD tdly1 tdly2 Figure 6. SE Pin Timing TELECOMMUNICATIONS 13 MC145423 SOIC PACKAGE PINOUT COMPARISON UDLT-3 PINOUT VERSUS MC145421DW/22DW/25DW/26DW (UDLT-1/UDLT-2 MASTER/SLAVE) PINOUT UDLT-3 MC145423 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK/8kHz SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ Tx EN2-TE2/SIE/ B1B2 EN1-TE1 MSI/TONE CCI/XTALin TDC-RDC/ XTALout LI SENS/ 2.048 MHz RE1/CLKOUT RE2/BCLK Rx LO2 LO1 MASTER/ SLAVE VDD 24 20 16 14 15 13 17 18 8 10 11 12 UDLT-1 Master MC145422 Pin No. 1 2 3 5 6 7 9 Pin Name VSS Vref LI LB VD SI1 SI2 Logic 0 High Impedance SO1 SO2 SE PD Logic 0 Tx SIE TE1 MSI CCI TDC/RDC Logic 0 LI SENS RE1 20 18 19 22 23 14 13 16 17 15 8 10 11 12 UDLT-1 Slave MC145426 Pin No. 1 2 3 5 6 7 9 Pin Name VSS Vref LI LB VD SI1 SI2 Logic 0 SDCLK SO1 SO2 Mu/A PD Logic 0 Tx B1B2 Logic 0 TE1 (Tone) TE (XTALin) X1 (XTALout) X2 2.048 MHz Out RE1 (BCLK) CLK Rx LO2 LO1 Logic 1 24 VDD 24 19 20 21 22 23 13 14 15 16 17 18 8 9 10 11 12 UDLT-2 Master MC145421 Pin No. 1 2 3 4 5 6 7 Pin Name VSS Vref LI LB VD D1I D2I Logic 1 DCLK D1O D2O SE PD Logic 1 Tx TE2 TE1 MSI CCI TDC/RDC Logic 0 LI SENS RE1 RE2 Rx LO2 LO1 Logic 0 VDD 24 19 20 21 22 23 13 14 15 16 17 18 8 9 10 11 12 UDLT-2 Slave MC145425 Pin No. 1 2 3 4 5 6 7 Pin Name VSS Vref LI LB VD DI1 DI2 Logic 1 DCLK D1O D2O (Mu/A) PD Logic 1 Tx EN2 EN1 TONE (XTALin) CCI (XTALout) XTL 2.048 MHz Out CLKOUT BCLK Rx LO2 LO1 Logic 1 VDD High Impedance 19 22 23 Rx LO2 LO1 Logic 0 VDD 14 TELECOMMUNICATIONS MC145423 MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE MC145423 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Name VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK/ 8kHz SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ Tx EN2-TE2/ SIE/B1B2 EN1-TE1 MSI/ TONE CCI/ XTALin TDC-RDC/ XTALout LI SENS/ 2.048 MHz RE1/ CLKOUT In/out Power Analog Ref Input Input Output Input Input Input Output Output Output Input I/O Input Output Input Output Input Input Output Output Output UDLT-1 Slave Mode Powered-Up Normal LB Low UDLT-1 Slave Mode Powered-Down TONE = 0, Off No Valid Burst Rec'd Valid Burst Rec'd TONE = 1, On No Valid Burst Rec'd Valid Burst Rec'd Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Gnd Gnd Gnd Gnd Gnd Gnd AGND VDD/2 Analog In 1 Digital Out 8 kbps Data In 8 kbps Data In 0 SDCLK/8kHz 8 kbps Data Out 8 kbps Data Out 1= Mu, 0=A 1 0 64 kbps Data Out 1/0 B1B2 EN1 = 8 kHz 1/0 TONE XTALin 4.096 MHz XTALout 4.096 MHz 2.048 MHz RE1 = 8 kHz AGND VDD/2 Analog In 0 Digital Out 8 kbps Data In 8 kbps Data In 0 SDCLK/8kHz 8 kbps Data Out 8 kbps Data Out 1= Mu, 0=A 1 0 64 kbps Data Out 1/0 B1B2 EN1 = 8 kHz 1/0 TONE XTALin 4.096 MHz XTALout 4.096 MHz 2.048 MHz RE1 = 8 kHz AGND VDD/2 Analog In Don't Care VD = 0 Don't Care Don't Care 0 High-Z, Not Used Data Not Changed Data Not Changed 1= Mu, 0=A 0 0 High Impedance 1/0 B1B2 EN1 = 0 TONE = 0 XTALin 4.096 MHz XTALout 4.096 MHz 2.048 MHz RE1 = 1 AGND VDD/2 Analog In Don't Care VD = 1 Don't Care Don't Care 0 High-Z, Not Used 8 kbps Data Out 8 kbps Data Out 1= Mu, 0=A 0 0 64 kbps Data Out 1/0 B1B2 EN1 = 8 kHz TONE = 0 XTALin 4.096 MHz XTALout 4.096 MHz 2.048 MHz RE1 = 8 kHz AGND VDD/2 Analog In Don't Care VD = 0 Don't Care Don't Care 0 High-Z, Not Used Data Not Changed Data Not Changed 1= Mu, 0=A 0 0 64 kbps PCM Tone 1/0 B1B2 EN1 = 8 kHz TONE = 1 XTALin 4.096 MHz XTALout 4.096 MHz 2.048 MHz RE1 = 8 kHz AGND VDD/2 Analog In Don't Care VD = 1 Don't Care Don't Care 0 High-Z, Not Used 8 kbps Data Out 8 kbps Data Out 1= Mu, 0=A 0 0 64 kbps PCM Tone 1/0 B1B2 EN1 = 8 kHz TONE = 1 XTALin 4.096 MHz XTALout 4.096 MHz 2.048 MHz RE1 = 8 kHz TELECOMMUNICATIONS 15 MC145423 MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE (continued) MC145423 Pin No. 23 24 25 26 27 28 Pin Name RE2/ BCLK Rx LO2 LO1 MASTER/ SLAVE VDD In/out Output Input Output Output Input Power UDLT-1 Slave Mode Powered-Up Normal BCLK = 128 kHz 64 kbps Data In Modulator Out Modulator Out 1 +V LB Low BCLK = 0 Don't Care Modulator Out Modulator Out 1 +V UDLT-1 Slave Mode Powered-Down TONE = 0, Off No Valid Burst Rec'd BCLK = 128 kHz Don't Care LO2 = LO1 LO1 = LO2 1 +V Valid Burst Rec'd BCLK = 128 kHz Don't Care LO2 = LO1 LO1 = LO2 1 +V TONE = 1, On No Valid Burst Rec'd BCLK = 128 kHz Don't Care LO2 = LO1 LO1 = LO2 1 +V Valid Burst Rec'd BCLK = 128 kHz Don't Care LO2 = LO1 LO1 = LO2 1 +V MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE MC145423 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ Tx EN2-TE2/ SIE/B1B2 In/out Power Analog Ref Input Input Output Input Input Input Normal Power Supply Gnd AGND VDD/2 Analog In 1 Digital out 8 kbps Data In 8 kbps Data In 0 UDLT-1 Master Mode Powered-Up LB Low Power Supply Gnd AGND VDD/2 Don't Care 0 Digital out 8 kbps Data In 8 kbps Data In 0 SE Low Power Supply Gnd AGND VDD/2 Analog In State Latched High Impedance State Latched State Latched 0 UDLT-1 Master Mode Powered-Down Normal Power Supply Gnd AGND VDD/2 Analog In Don't Care Digital out 8 kbps Data In 8 kbps Data In 0 SE Low Power Supply Gnd AGND VDD/2 Analog In Don't Care High Impedance State Latched State Latched 0 Don't Care High Impedance High Impedance High Impedance High Impedance High Impedance Output Output Input Input Input Output Input 8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance 8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance 1 1 0 64 kbps Data Out SIE Digital In 1 1 0 64 kbps Data Out SIE Digital In 0 State Latched 0 64 kbps Data Out SIE Digital In 1 0 0 64 kbps Data Out SIE Digital In 0 State Latched 0 64 kbps Data Out SIE Digital In 16 TELECOMMUNICATIONS MC145423 MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE (continued) MC145423 Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name EN1-TE1 MSI/TONE CCI/ XTALin TDC-RDC/ XTALout LI SENS/ 2.048 MHz RE1/ CLKOUT RE2/ BCLK Rx LO2 LO1 MASTER/ SLAVE VDD In/out Input Input Input Input Input Input Normal TE1 8 kHz MSI 8 kHz CCI 2.048 MHz TDC-RDC Data Clk Digital In LI Sensitivity RE1 8 kHz UDLT-1 Master Mode Powered-Up LB Low TE1 8 kHz MSI 8 kHz CCI 2.048 MHz TDC-RDC Data Clk Digital In LI Sensitivity RE1 8 kHz SE Low TE1 8 kHz MSI 8 kHz CCI 2.048 MHz TDC-RDC Data Clk Digital In LI Sensitivity RE1 8 kHz UDLT-1 Master Mode Powered-Down Normal TE1 8 kHs MSI 8 kHz CCI 2.048 MHz TDC-RDC Data Clk Digital In LI Sensitivity RE1 8 kHz SE Low TE1 8 kHz MSI 8 kHz CCI 2.048 MHz TDC-RDC Data Clk Digital In LI Sensitivity RE1 8 kHz Don't Care High Impedance High Impedance High Impedance High Impedance High Impedance Input Output Output Input Power 64 kbps Data In Modulator Out Modulator Out 0 +V 64 kbps Data In LO2 = LO1 LO1 = LO2 0 +V 64 kbps Data In No Effect No Effect 0 +V Don't Care LO2 = LO1 LO1 = LO2 0 +V Don't Care LO2 = LO1 LO1 = LO2 0 +V MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE UDLT-2 Slave Mode Powered-Up In/out Power Analog Ref Input Input Output Input Input Input Output Normal LB Low UDLT-2 Slave Mode Powered-Down TONE = 0, Off No Valid Burst Rec'd Valid Burst Rec'd TONE = 1, On No Valid Burst Rec'd Valid Burst Rec'd MC145423 Pin No. 1 2 3 4 5 6 7 8 9 Pin Name VSS Vref LI LB VD SDI1 SDI2 FRAME 10/20 SDCLK Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Gnd Gnd Gnd Gnd Gnd Gnd AGND VDD/2 Analog In 1 Digital Out 16 kbps Data In 16 kbps Data In 1 16 kHz AGND VDD/2 Analog In 0 Digital Out 16 kbps Data In 16 kbps Data In 1 16 kHz AGND VDD/2 Analog In Don't Care VD = 0 Don't Care Don't Care 1 16 kHz AGND VDD/2 Analog In Don't Care VD = 1 Don't Care Don't Care 1 16 kHz AGND VDD/2 Analog In Don't Care VD = 0 Don't Care Don't Care 1 16 kHz AGND VDD/2 Analog In Don't Care VD = 1 Don't Care Don't Care 1 16 kHz TELECOMMUNICATIONS 17 MC145423 MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE (continued) UDLT-2 Slave Mode Powered-Up In/out Output Output Input I/O Input Output Output Output Input Input Output Output Output Output Input Output Output Input Power Normal 16 kbps Data Out 16 kbps Data Out 1/0 Mu/A 1 1 128 kbps Data Out* EN2 8 kHz EN1 8 kHz 1/0 Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 8 kHz BCLK 128 kHz 128 kbps Data In Modulator Out Modulator Out 1 +V LB Low 16 kbps Data Out 16 kbps Data Out 1/0 Mu/A 1 1 128 kbps Data Out* EN2 8 kHz EN1 8 kHz 1/0 Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 8 kHz BCLK = 0 Don't Care Modulator Out Modulator Out 1 +V UDLT-2 Slave Mode Powered-Down TONE = 0, Off No Valid Burst Rec'd Data Not Changed Data Not Changed 1/0 Mu/A 0 1 High Impedance EN2 = 0 EN1 = 0 0 No Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 0 BCLK 128 kHz Don't Care LO2 = LO1 LO2 = LO1 1 +V Valid Burst Rec'd 16 kbps Data Out 16 kbps Data Out 1/0 Mu/A 0 1 64 kbps Data Out EN2 = 0 EN1 = 0 0 No Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 0 BCLK 128 kHz Don't Care LO2 = LO1 LO2 = LO1 1 +V TONE = 1, On No Valid Burst Rec'd Data Not Changed Data Not Changed 1/0 Mu/A 0 1 500 Hz Tone Out EN2 8 kHz EN1 8 kHz 1 No Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 8 kHz BCLK 128 kHz 128 kbps Data In LO2 = LO1 LO1 = LO2 1 +V Valid Burst Rec'd 16 kbps Data Out 16 kbps Data Out 1/0 Mu/A 0 1 500 Hz Tone Out EN2 8 kHz EN1 8 kHz 1 Tone XTAL 8.192 MHz XTAL 8.192 MHz 2.048 MHz RE1 8 kHz BCLK 128 kHz 128 kbps Data In LO2 = LO1 LO1 = LO2 1 +V MC145423 Pin No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name SDO1 SDO2 SE/ (Mu/A) PD MOD TRI/SQ Tx EN2-TE2/ SIE/B1B2 EN1-TE1 MSI/ TONE CCI/ XTALin TDC-RDC/ XTALout LI SENS/ 2.048 MHz RE1/ CLKOUT RE2/ BCLK Rx LO2 LO1 MASTER/ SLAVE VDD * Tx is high impedance when TE1 and TE2 are both low, simultaneously. Tx is undefined when TE1 and TE2 are both high, simultaneously. 18 TELECOMMUNICATIONS MC145423 MC145423 UDLT-3 PIN STATES FOR UDLT-2 MASTER MODE MC145423 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name VSS Vref LI LB VD SDI1 SDI2 FRAME 10/ 20 SDCLK SDO1 SDO2 SE/(Mu/A) PD MOD TRI/SQ Tx EN2-TE2/ SIE/B1B2 EN1-TE1 MSI/TONE CCI/XTALin TDC-RDC/ XTALout LI SENS/ 2.048 MHz RE1/ CLKOUT RE2/BCLK Rx LO2 LO1 MASTER/ SLAVE VDD In/out Power Analog Ref Input Input Output Input Input Input Input Output Output Input Input Input Output Input Input Input Input Input Input Input Input Input Output Output Input Power UDLT-2 Master Powered-Up Normal Power Supply Gnd AGND VDD/2 Analog In 1 Digital Out 16 kbps Data In 16 kbps Data In 1 16 kHz 16 kbps Data Out 16 kbps Data Out 1 1 1 128 kbps* Data Out TE2 8 kHz TE1 8 kHz 8 kHz CCI 4.096 MHz TDC-RDC Data Clk Digital In Sensitivity RE1 8 kHz RE2 8 kHz LB Low Power Supply Gnd AGND VDD/2 Don't Care 0 Digital Out 16 kbps Data In 16 kbps Data In 1 16 kHz 16 kbps Data Out 16 kbps Data Out 1 1 1 128 kbps* Data Out TE2 8 kHz TE1 8 kHz 8 kHz CCI 4.096 MHz TDC-RDC Data Clk Digital In Sensitivity RE1 8 kHz RE2 8 kHz SE Low Power Supply Gnd AGND VDD/2 Analog In State Latched High Impedance State Latched State Latched 1 16 kHz High Impedance High Impedance 0 State Latched 1 128 kbps* Data Out TE2 8 kHz TE1 8 kHz 8 kHz CCI 4.096 MHz TDC-RDC Data Clk Digital In Sensitivity RE1 8 kHz RE2 8 kHz UDLT-2 Master Powered-Down Normal Power Supply Gnd AGND VDD/2 Analog In Don't Care Digital Out 16 kbps Data In 16 kbps Data In 1 16 kHz 16 kbps Data Out 16 kbps Data Out 1 0 1 128 kbps* Data Out TE2 8 kHz TE1 8 kHz 8 kHz CCI 4.096 MHz TDC-RDC Data Clk Digital In Sensitivity RE1 8 kHz RE2 8 kHz Don't Care LO2 = LO1 LO1 = LO2 0 +V SE Low Power Supply Gnd AGND VDD/2 Analog In Don't Care High Impedance State Latched State Latched 1 16 kHz High Impedance High Impedance 0 State Latched 1 128 kbps* Data Out TE2 8 kHz TE1 8 kHz 8 kHz CCI 4.096 MHz TDC-RDC Data Clk Digital In Sensitivity RE1 8 kHz RE2 8 kHz Don't Care LO2 = LO1 LO1 = LO2 0 +V 128 kbps Data In 128 kbps Data In 128 kbps Data In Modulator Out Modulator Out 0 +V LO2 = LO1 LO1 = LO2 0 +V No Effect No Effect 0 +V * Tx is high impedance when TE1 and TE2 are both low, simultaneously. Tx is undefined when TE1 and TE2 are both high, simultaneously. TELECOMMUNICATIONS 19 MC145423 PIN DESCRIPTIONS VSS Negative Supply (Pin 1) This is the most negative power pin, and should be tied to system ground (0 V). Vref Voltage Reference Output (Pin 2) This is the output from the internal reference supply (mid-supply) and should be bypassed to both VSS and VDD with 0.1 F capacitors. This pin usually serves as an analog ground reference for transformer coupling of the device's incoming bursts from the line. No external load should be placed on this pin. LI Line Input (Pin 3) This pin is the input to the demodulator for the incoming bursts. This input has an internal 240 k resistor tied to the Vref pin, so an external capacitor or line transformer may be used to couple the input signal to the device with no dc offset. LB Loopback Low Input (Pin 4) Master Mode: A low on this pin ties the internal modulator output to the internal demodulator input, which loops the entire burst for testing purposes. During the loopback operation, the LI input is ignored, and the LO1 and LO2 outputs are driven to equal voltages. The state of the LB pin is internally latched if the SE pin is held low. This feature is only active when the PD input is high. Slave Mode: When this pin is low and PD is high, the incoming B channels from the master are burst back to the master, instead of the Rx B channel input data. The SDI1 and SDI2 functions operate normally in this mode, and the BCLK (pin 23) is held low. Additionally, for both the UDLT-1 and UDLT-2 mode, when the TONE (pin 18) and loopback functions are active simultaneously, the loopback function overrides the TONE function. VD Valid Data Output (Pin 5) A high level on this pin indicates that a valid line transmission has been demodulated. A valid line transmission burst is determined by proper synchronization and the absence of detected bit errors. VD is a CMOS output and is high impedance when SE is low. Master Mode: VD changes state on the rising edge of MSI, when PD is high. When PD is low, VD changes state at the end of demodulation of a transmission burst and does not change again until three MSI rising edges have occurred, at which time it goes low, or until the next demodulation of a burst. Slave Mode: If no transmissions from the master have been received within the last 250 s, as determined by an internal oscillator, VD will go low. SDI1 and SDI2 D Channel Signaling Data Bit Inputs 1 and 2 (Pins 6 and 7) Master Mode (UDLT-1): These inputs are the 8 kbps serial data inputs in UDLT-1 mode. Data on these pins is loaded on the rising edge of MSI for transmission to the slave. The state of these pins is latched if SE is held low. Slave Mode (UDLT-1): These inputs are the 8 kbps serial data inputs in UDLT-1 mode. Data on these pins is loaded on the rising edge of TE1 for transmission to the master. If no transmissions from the master are being received and PD is high, data on these pins will be loaded into the part on an internal signal. Therefore, data on these pins should be steady until synchronous communication with the master has been established, as indicated by the high on VD. Master Mode (UDLT-2): These inputs are the 16 kbps serial data inputs in UDLT-2 mode. Two bits should be clocked into each of these inputs between the rising edges of the MSI frame reference clock. The first bit of each D channel is clocked into an intermediate buffer on the first falling edge of the SDCLK following the rising edge of MSI. The second bit of each D channel is clocked in on the next negative transition of the SDCLK. If further SDCLK negative edges occur, new information is serially clocked into the buffer replacing the previous data, one bit at a time. Buffered D channel bits are burst to the slave on the next rising edge of the MSI frame reference clock. The state of these pins is latched if SE is held low. Slave Mode (UDLT-2): These inputs are the 16 kbps serial data inputs in UDLT-2 mode. The D channel data bits are clocked in serially on the negative edge of the 16 kbps SDCLK output pin. 20 TELECOMMUNICATIONS MC145423 FRAME 10/20 (Pin 8) The UDLT series of transceivers are designed to operate using a ping-pong transmission scheme with an 8 kHz burst rate. Each frame the master device "pings" a burst of data to the slave, which responds with a "pong" burst of data. This pin selects whether this 8 kHz frame will have a 10-bit data burst for UDLT-1 compatibility or a 20-bit data burst for UDLT-2 compatibility. A logic low (0 V) selects the UDLT-1 (MC145422/ MC145426) mode. This sets the device to operate with one 64 kbps voice/data channel and two 8 kbps signaling channels. A logic high (VDD) on this pin selects the UDLT-2 (MC145421/MC145425) mode. This sets the device to operate with two 64 kbps channels and two 16 kbps channels (2B+2D). SDCLK D Channel Signaling Data Clock Input (Pin 9) Master Mode (UDLT-2): This is the transmit and receive data clock input for both D channels. See SDO1 and SDO2 pin descriptions for more information. Master Mode (UDLT-1): High impedance. Slave Mode (UDLT-2): This is the transmit and receive data clock output for both D channels. It starts on demodulation of a burst from the master device. This signal is rising-edge aligned with the EN1 and BCLK signals. After the demodulation of a burst, the SDCLK line completes two cycles and then remains low until the next burst from the master is demodulated. In this manner, synchronization with the master is established and any clock slip between master and slave is absorbed each frame. Slave Mode (UDLT-1): This pin outputs 8 kHz equivalent to TE1. SDO1 and SDO2 D Channel Signaling Data Outputs 1 and 2 (Pins 10 and 11) Master Mode (UDLT-2): These serial outputs provide the 16 kbps D channel signaling information from the incoming burst. Two data bits should be clocked out of each of these two outputs between the rising edges of the MSI frame reference clock. The rising edge of MSI produces the first bit of each D channel on its respective pin. Circuitry then searches for a negative D channel clock edge. This tells the D channel data shift register to produce the second D channel bit on the next rising edge of the SDCLK. Further rising edges of the SDCLK recirculate the D channel output buffer information. Master Mode (UDLT-1): These outputs are received signaling bits from the slave UDLT and change state on the rising edge of MSI, if PD is high; or at the end of demodulation, if PD is low. Slave Mode (UDLT-2): These two pins are the outputs for the 16 kbps D channels. These pins are updated on the rising edges of the slave SDCLK output pin. Slave Mode (UDLT-1): These outputs are received signaling bits from the master UDLT and change state on the rising edge of TE1. SE/(Mu/A) Signaling Enable Input or Tone Format Input (Pin 12) Master Mode (SE): A low on this pin causes the state of LB, PD, SDI1, and SDI2 to be stored. Additionally, output pins VD, SDO1, and SDO2 will be high impedance. This allows the device to be bussed with other UDLTs using a common control bus. A high on this pin returns the device to normal operation. Slave Mode (Mu/A): This pin allows the user to select the PCM code format for the pacifier tone. A high on this pin selects Mu-Law. A low on this pin selects A-Law. The state of this pin determines the PCM code sequence for the 500 Hz square wave tone generated when the TONE pin input is high. PD Power Down Low (Pin 13) Master Mode: When this pin is held low, the device powers down, except for the circuitry necessary to demodulate an incoming burst and to output VD and the B and D channel data bits. When this pin is brought high, the device waits for three positive MSI edges or until the end of an incoming transmission from the slave and then begins transmitting every MSI period to the slave UDLT on the next rising edge of MSI. Slave Mode: This is a bidirectional pin with a weak output driver that can be externally overdriven. When this pin is floating and a burst from the master is demodulated, the weak output drivers will try to force PD high. The drivers will try to force PD low, if TELECOMMUNICATIONS 21 MC145423 250 s have elapsed without a burst from the master being successfully demodulated. This allows the slave device to self power-up and power-down in demand powered loop systems. When held low, the device powers down and the only active circuitry, is that which is necessary for the demodulation of data. When held high, the device is powered up and transmits normally in response to received bursts from the master. MOD TRI/SQ Modulation Select (Pin 14) A logic low (0 V) on this pin selects the MDPSK modulation which has a slew controlled voltage output for reduced EMI/RFI. This output looks like a triangle waveform that is modulated with different angles for the peaks. A logic high (VDD) on this pin, selects square wave output for maximum power to the line. Tx Transmit Data Output (Pin 15) Master Mode (UDLT-1): This pin is high impedance when TE1 is low. When TE1 is high, this pin presents new 8-bit B channel data on rising edges of TDC-RDC. Slave Mode (UDLT-1): B channel data is output on this pin on the rising edge of BCLK, while TE1 is high. This pin is high impedance when TE1 is low. Master Mode (UDLT-2): This pin is high impedance when both TE1 and TE2 are low. This pin serves as an output for B channel information received from the slave device. The B channel data is under control of TE1 and TE2 and TDC-RDC. Slave Mode (UDLT-2): This pin is an output for the B channel data received from the master. B channel 1 data is output on the first eight cycles of the BCLK output when EN1 is high. B channel 2 data is output on the next eight cycles of the BCLK, when EN2 is high. B channel data bits are clocked out on the rising edge of the BCLK output pin. EN2-TE2/SIE/B1B2 B Channel 2 Enable Output or Signal Insert Enable (Pin 16) Master Mode (SIE UDLT-1): In this mode, this pin functions as SIE. When held high, this pin causes signal bit 2, as received from the slave, to be inserted into the LSB of the outgoing PCM word at the Tx pin. The SDI2 pin will be ignored, and in its place, the LSB of the incoming word at the Rx pin will be transmitted to the slave. The PCM word to the slave will have LSB forced low in this mode. In this manner, signal bit 2 to/ from the slave UDLT is inserted into the PCM words the master sends and receives from the backplane, for routing through the PABX for simultaneous voice/data communication. The state of this pin is internally latched if the SE pin is brought and held low. Slave Mode (UDLT-1): In this mode, this pin is an input and selects the timeslot used for transferring the receive data word. When this pin is low, the device uses the RE1 pin timing the same as the MC145426 UDLT-1 slave. When this pin is a logic 1, the receive word is latched in during the TE1 timeslot, simultaneously with the transmit word transfer. The RE1 pin timing is not affected by this selection. Master Mode (EN2-TE2 UDLT-2): In this mode, this pin functions as EN2-TE2. This pin, along with TE1 pin-17 control the output of data for their respective B-channel on the Tx output pin. When both TE1 and TE2 are low, the Tx pin is high impedance. The rising edge of the respective enable produces the first bit of the selected B-channel data on the Tx pin. Internal circuitry then scans for the next negative transition of the TDC-RDC clock. Following this event, the next seven bits of the selected B-channel data are output on the next seven rising edges of the TDC-RDC data clock. When TE1 and TE2 are high simultaneously, data on the Tx pin is undefined. TE1 and TE2 should be approximately leading-edge aligned with the TDC-RDC data clock. To keep the Tx pin out of the high impedance state, these enable lines should be high while the respective B channel data is being output. Slave Mode (EN2-TE2 UDLT-2): Functioning as EN2-TE2, this pin is an output and serves as an 8 kHz enable signal for the input and output of the B channel 2 data. While EN2 is high, B channel 2 data is clocked out on the Tx pin on the eight rising edges of the BCLK. During this same time, B channel 2 input data is clocked in on the Rx pin, on the eight falling edges of the BCLK. EN1-TE1 B Channel 1 Enable Output (Pin 17) This pin is the logical inverse of EN2-TE2, and serves to control B channel 1 data. See the above pin description for more information. EN1 serves as the slave device's 8 kHz frame reference signal. The VD 22 TELECOMMUNICATIONS MC145423 pin is also updated on the rising edge of the EN1 signal. MSI/TONE Master Sync Input or Tone Enable Input (Pin 18) Master Mode (MSI): This pin is the master 8 kHz frame reference input. The rising edge of MSI loads B and D channel data, which had been input during the previous frame, into the modulator section of the device, and initiates the outbound burst onto the twisted pair cable. The rising edge of MSI also initiates the buffering of the B and D channel data demodulated during the previous frame. MSI should be approximately leading edge aligned with the TDCRDC data clock input signal. Slave Mode (TONE): A high on this pin causes a 500 Hz square wave PCM tone to be inserted in place of the demodulated data. This feature allows the designer to provide audio feedback for telset keyboard depressions. CCI/XTALin Convert Clock Input or Crystal Input (Pin 19) Master Mode (CCI UDLT-1): A 2.048 MHz clock signal should be applied to this pin. This signal is used for internal sequencing and control. This signal should be frequency and phase coherent with MSI for optimum performance. Slave Mode (XTALin UDLT-1): A 4.096 MHz crystal is tied between this pin and XTALout (pin 20). A 10 M resistor across this pin and XTALout and 25 pF capacitors from this pin and XTALout to VSS are required for stability and to ensure start-up. This pin may be driven from an external source. XTALout should be left open if an external signal is used on this input. Master Mode (CCI UDLT-2): An 8.192 MHz clock should be supplied to this input. The 8.192 MHz input should be 50% duty cycle. This signal may free run with respect to all other clocks without performance degradation. Slave Mode (XTALin UDLT-2): Normally, an 8.192 MHz crystal is tied between this pin and the XTALout (pin 20). A 10 M resistor between XTALin and XTALout and 25 pF capacitors from XTALin and XTALout to VSS are required to ensure stability and start-up. XTALin may also be driven with an external 8.192 MHz signal if a crystal is not desired. XTALout should be left open if an external signal is used on this input. TDC-RDC/Xtalout Transmit and Receive Data Clock or Crystal Output (Pin 20) Master Mode (TDC-RDC): This input is the transmit and receive data clock for the B channel data. Output data changes state on the rising edge of this signal, and input data is read on the falling edges of this signal. TDC-RDC should be roughly leading edge aligned with MSI. Slave Mode (XTALout): This pin is the crystal out pin. It is capable of driving one external CMOS input and 15 pF of additional capacitance. See pin description for XTALin (pin 19). LI SENS/2.048 MHz Line Input Sensitivity or 2.048 MHz Output (Pin 21) Master Mode: By applying a logic 1 on this pin, the sensitivity of LI is reduced by 15 dB. This reduces the effects of crosstalk, and false detects that would be picked up and demodulated when the LI pin is connected to an open loop. Slave Mode: This pin outputs a 2.048 MHz signal for use with a PCM codec-filter. All other device clocks are generated from the rising edge of this clock. The 8 kHz enables are derived by dividing this 2.048 MHz clock by a nominal ratio of 256. Phase synchronization to the master UDLT's burst is achieved by dividing this clock by the ratios of either 255, 256, or 257. RE1/CLKOUT Receive Data Enable 1 Input or Clock Output (Pin 22) Master Mode (RE1 UDLT-1): A rising edge on this pin will enable data on the Rx pin to be loaded into the receive data register on the next eight falling edges of the TDC-RDC data clock. RE1 and TDCRDC should be approximately leading edge aligned. Slave Mode (RE1 UDLT-1): This B series CMOS output is the inverse of TE1 (see TE1 pin description). Master Mode (RE1 UDLT-2): This input along with RE2 (pin 23) control the input of B channel data on the Rx pin. The rising edge of the respective enable signal causes the device to load the selected receive TELECOMMUNICATIONS 23 MC145423 data buffer with data from the Rx pin on the next eight falling edges of the TDC-RDC clock. The RE1 and RE2 enables should be roughly leading edge aligned with the TDC-RDC data clock. These enables are rising edge sensitive and need not be high for the entire B channel input period. Slave Mode (CLKOUT UDLT-2): This pin serves as a buffered output of the crystal frequency divided by two. RE2/BCLK Receive Data Enable Input 2 or B Channel Data Clock Output (Pin 23) Master Mode (UDLT-1): This pin is high impedance. Master Mode (RE2 UDLT-2): See pin description for RE1 (pin 22). Slave Mode (BCLK UDLT-1 and UDLT-2): This output provides the data clock for the telset codec-filter. This clock signal is 128 kHz and begins operating upon the successful demodulation of a burst from the master. At this time, EN1-TE1 goes high and BCLK starts toggling. BCLK remains active for 16 periods, at the end of which time it remains low until another burst is received from the master. In this manner, synchronization between the master and slave is established and any clock slippage is absorbed each frame. If TONE (pin 18) is brought high, then EN1TE1/RE1 are generated from an internal oscillator until TONE is brought low, or an incoming burst from the master is received. BCLK is disabled when LB is held low. Rx Receive Data Input (Pin 24) Master Mode (UDLT-1): The 8-bit B channel data is clocked into the device on this pin, on the falling edges of TDC-RDC, under the control of RE1. Slave Mode (UDLT-1): The 8-bit B channel data from the telset PCM codec-filter is input on this pin on the eight falling edges of BCLK after RE1 goes high, when EN2-TE2/SIE/B1B2, pin 16 is low. When EN2TE2/SIE/B1B2, pin16 is high, the receive data word is latched in during the high period of EN1-TE1, pin 17 which is simultaneous with the transfer of the transmit word. See the pin descriptions for EN2-TE2/SIE/ B1B2 and EN1-TE2 for more information. Master Mode (UDLT-2): B channel data is input on this pin and controlled by the RE1, RE2, and TDCRDC pins. Slave Mode (UDLT-2): This pin is an input for the B channel data. B channel 1 data is clocked in on the first eight falling edges of the BCLK output following the rising edge of the EN1 output. B channel 2 data is clocked in on the next eight falling edges of the BCLK following the rising edge of the EN2 output. LO2 Line Drive Output (Pin 25) The LO2 pin, along with LO1 (pin 26) form a pushpull output, to drive the twisted pair transmission line. The UDLT-1 drives the twisted pair with a 10-bit, 256 kHz modified DPSK (MDPSK) burst, or a square wave (set by pin 14 MOD TRI/SQ) burst, each 125 s. The UDLT-2 drives the twisted pair with a 20-bit 512 kHz modulated burst. When these pins are idle and set for square wave modulation, they rest at the positive power supply voltage. When these pins are idle and set for MDPSK, they rest at Vref. For power supply voltages less than 4.5 V, squarewave modulation must be used. LO1 Line Driver Output (Pin 26) See the pin description for LO2 (pin 25). MASTER/SLAVE Master/Slave Mode (Pin 27) A logic low (0 V) on this pin selects master and a logic high (VDD) selects slave. VDD Positive Supply (Pin 28) This is the most positive power supply pin. Acceptable operating voltages are from 4.5 V to 5.5 V. 24 TELECOMMUNICATIONS BASIC DIGITAL TELSET 5V 5V DR 4.7 k N=4 5V 5V N = 0.5 4.7 k FSR DT Rx RE1/CLKout RE2/BCLK LI Vref VD MASTER/SLAVE LO1 LO2 MOD TRI/SQ SE/(Mu/A) SDI1 FRAME 10/20 VSS 110 110 N=2 110 110 N = 0.5 RING SDI2 EN2-TE2 (I/O)/SIE 0.01 F SDO1 SDO2 SDCLK LB Tx EN1-TE1 (I/O) PD VDD VDD Mu/A PD RO- PI PO- PO+ TG TI- TI+ VSS 0.1 F 75 k 1 k 420 pF 100 k 4.096 MHz DTMF OUT OP 10 V 10 k 4.7 F SPEAKER OSCin OCSout 3.58 MHz 1.8 k 10 V LM317 270 5V 4.7 F 78M05 50 F OH/T TSO MO MS 33 V 2W 20 pF 20 pF 20 TDC-RDC/XTALout 10 M MSI/TONE 2.048 MHz CCI/XTALin MCLK VAG VAG-REF MC145423 UDLT-3 SLAVE MODE MC145484 FST BCLKT BCLKR TIP REC 5V 1 k 68 F 1 k 1.0 F 1 k MIC TELECOMMUNICATIONS 1.0 F 5V VDD ROW & COL KEYPAD PULSE TONE DIALER VSS MC145423 25 MC145423 MULTICHANNEL DIGITAL LINE CARD POWER SUPPLY TIP VDD LO1 Vref LO2 LI SDI1 SDI2 SDO1 SDO2 SDCLK RE2/BCLK LI SENS/2.048 MHz LB VD MSI/TONE Tx Rx TDC/RDC/XTALout CCI/XTALin UDLT-3 PD MASTER RE1/CLKOUT MODE EN1-TE1 (I/O) EN2-TE2(I/O)/SIE SE/(Mu/A) MASTER/SLAVE MOD SELECT FRAME 10/20 VSS 8 kHz FRAME SYNC TRANSMIT DATA BUS RECEIVE DATA BUS 2.048 MHz DATA CLOCK TO BACKPLANE RING TO BACKPLANE TIMING AND CONTROL POWER SUPPLY TIP VDD LO1 Vref LO2 LI SDI1 SDI2 MSI/TONE Tx Rx TDC/RDC/XTALout CCI/XTALin UDLT-3 PD MASTER RE1/CLKOUT MODE EN1-TE1 (I/O) SDO1 EN2-TE2(I/O)/SIE SDO2 SDCLK RE2/BCLK LI SENS/2.048 MHz LB VD RING SE/(Mu/A) MASTER/SLAVE MOD SELECT FRAME 10/20 VSS 26 TELECOMMUNICATIONS MC145423 PACKAGE DIMENSIONS DW SUFFIX SOIC PACKAGE CASE 751F-05 A D 28 15 M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0 8 E H 1 14 PIN 1 IDENT B 0.25 M B L 0.10 e B 0.025 M C C SEATING PLANE DIM A A1 B C D E e H L CA S B A1 S A TELECOMMUNICATIONS 27 MC145423 DT SUFFIX TSSOP PACKAGE CASE 1168-01 D 28 15 B C A A b1 c c1 E/2 E E1 (b) SECTION A-A 1 14 2X PIN 1 INDEX 0.2 A B C e/2 26X e 2X 14 TIPS VIEW A END VIEW TOP VIEW 0.05 (D) 28X 0.2 A NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. 4. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR MOLD PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 PER SIDE. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.38. MILLIMETERS MIN MAX --1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.19 0.25 0.09 0.20 0.09 0.16 9.60 9.80 0.65 BSC 6.40 BSC 4.30 4.50 0.50 0.70 0 8 14 REF SEATING PLANE A 28X b 0.1 M A B C GAGE PLANE A1 A2 A ( 1) SIDE VIEW 0.25 L VIEW A DIM A A1 A2 b b1 c c1 D e E E1 L 1 28 TELECOMMUNICATIONS MC145423 Digital DNA is a trademark of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://motorola.com/semiconductors/ MC145423/D |
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